The present invention relates to an insulated gate field effect transistor (hereinafter abbreviated to IGFET).
To avoid an unfavorable lateral extension of a depletion layer from a drain region into a channel region when a drain voltage (drain bias) is applied, an impurity region having the same conductivity type as and a higher impurity concentration than the substrate is formed in the channel region between drain and source regions. The technology is described, for example, in U.S. Pat. No. 3,745,425. On the other hand, when the IGFET is of a type having a short channel (1 .mu.m or less) thereby forming a shallow source, drain region, the impurity region having the higher impurity concentration and formed in the channel region is also formed inevitably under the bottom of the drain region deeply from the bottom. The IGFET can be prevented from a punch-trough phenomenon by the lateral extension of the depletion layer mentioned above because the impurity region of high impurity concentration is provided in the channel region, that is, in a portion of the substrate between the sides of the source and drain regions facing each other. However, at the bottom of the drain region, an extension of the depletion layer is also suppressed. Therefore, the output capacitance of the IGFET due to the PN junction at the bottom of drain region becomes a high level during the operation by applying the drain voltage so that the IGFET has its high-speed operation adversely affected.